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3603497a13
GreemDev-Ryujinx
/
ChocolArm64
/
Decoder
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gdkchan
980691f36b
[CPU] Fix CBZ/CBNZ with 32 bits operands
2018-04-06 17:22:26 -03:00
..
ABlock.cs
ACond.cs
ADataOp.cs
ADecoder.cs
Improve CPU initial translation speeds (
#50
)
2018-03-04 14:09:59 -03:00
ADecoderHelper.cs
AIntType.cs
AOpCode.cs
AOpCodeAdr.cs
AOpCodeAlu.cs
AOpCodeAluImm.cs
AOpCodeAluRs.cs
AOpCodeAluRx.cs
AOpCodeBfm.cs
AOpCodeBImm.cs
AOpCodeBImmAl.cs
AOpCodeBImmCmp.cs
[CPU] Fix CBZ/CBNZ with 32 bits operands
2018-04-06 17:22:26 -03:00
AOpCodeBImmCond.cs
AOpCodeBImmTest.cs
AOpCodeBReg.cs
AOpCodeCcmp.cs
AOpCodeCcmpImm.cs
AOpCodeCcmpReg.cs
AOpCodeCsel.cs
AOpCodeException.cs
AOpCodeMem.cs
AOpCodeMemEx.cs
AOpCodeMemImm.cs
AOpCodeMemLit.cs
AOpCodeMemPair.cs
AOpCodeMemReg.cs
AOpCodeMov.cs
AOpCodeMul.cs
AOpCodeSimd.cs
Fix cpu issue with cmp optimization, add HINT and FRINTX (scalar) instructions, fix for NvFlinger sometimes missing free buffers
2018-02-24 11:19:28 -03:00
AOpCodeSimdCvt.cs
AOpCodeSimdExt.cs
Add SMLAL (vector), fix EXT instruction
2018-03-06 21:36:49 -03:00
AOpCodeSimdFcond.cs
AOpCodeSimdFmov.cs
AOpCodeSimdImm.cs
CPU fix for the cases using a Mask with shift = 0
2018-03-14 01:59:22 -03:00
AOpCodeSimdIns.cs
AOpCodeSimdMemImm.cs
AOpCodeSimdMemLit.cs
AOpCodeSimdMemMs.cs
Enable all ld/st (single structure) instructions
2018-03-30 18:06:02 -03:00
AOpCodeSimdMemPair.cs
AOpCodeSimdMemReg.cs
AOpCodeSimdMemSs.cs
Enable all ld/st (single structure) instructions
2018-03-30 18:06:02 -03:00
AOpCodeSimdReg.cs
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
2018-03-05 16:18:37 -03:00
AOpCodeSimdRegElem.cs
Add MLA (vector by element), fixes some cases of MUL (vector by element)?
2018-03-15 22:36:47 -03:00
AOpCodeSimdRegElemF.cs
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
2018-03-05 16:18:37 -03:00
AOpCodeSimdShImm.cs
AOpCodeSimdTbl.cs
AOpCodeSystem.cs
AShiftType.cs
IAOpCode.cs
IAOpCodeAlu.cs
IAOpCodeAluImm.cs
IAOpCodeAluRs.cs
IAOpCodeAluRx.cs
IAOpCodeCond.cs
IAOpCodeLit.cs
IAOpCodeSimd.cs